Generally, the speed at which an integrated circuit operates is influenced by the distance between the farthest separated components that communicate with each other on the chip. Stacking dies as three-dimensional structures has been shown to significantly reduce the communication path length between components on different dies, provided the vertical distances between the dies are much smaller than the die size of the individual die. Thus, by stacking dies vertically, the overall system speed is typically increased. One method that has been used to implement such stacking structure is through wafer bonding.
Wafer bonding is the joining together of two or more semiconductor wafers on which integrated circuitry has been formed. Wafers are typically joined by direct bonding of external oxide layers or by adding adhesives to external dielectric layers. The bonded result produces a three-dimensional wafer stack which is subsequently diced into separate “stacked die,” with each individual stacking die structure having multiple layers of integrated circuitry. In addition to the increased system speed that the three-dimensional circuitry typically experiences, wafer stacking offers other potential benefits, including improved form factors, lower costs, and greater integration through system-on-chip (SOC) solutions. In order to enable the various components integrated within each stacking die structure, electrical connections, such as through-silicon vias (TSVs) are typically formed to provide conductors between vertical dies. TSVs are typically fabricated to provide vias filled with a conducting material that passes completely through a die to contact and connect with the other TSVs and conductors of the stacking die structure.
In an existing TSV formation process, TSV recesses are formed after the CMOS device formations in a wafer substrate and after the metallization process of forming metal traces in the inter-metal dielectric layers. In an IC fabricated with advanced processing technology, the inter-metal dielectric layers are typically formed with dielectric materials having low dielectric constant (low-k) or extremely low dielectric constant in an effort to reduce inter-metal layer parasitic capacitance, thus increasing signal speed and enhance signal integrity. As an example, a low-k dielectric material has a dielectric constant less than 2.9, and is formed with a porous organic dielectric material.
The TSV recesses formed in the inter-metal dielectric layers and in the substrate are subsequently filled with conductive metallic materials by a metallization process, such as a metallic chemical vapor deposition process (CVD) or a metal electroplating process. In order to facilitate the formation, a TSV recess typically has a large size with a large exposed surface area. This TSV formation process creates a number of problems in advanced processing technologies. One of the problems is that the formation of the TSV recesses in the inter-metal dielectric layers typically involves multiple etch processes; the wafers under processing often stand in queue for the various etch process to be completed. During processing, moisture or other chemical agents in a wafer processing facility may leach into the low-k inter-metal dielectric layers from the side wall of the TSV recesses and diffuse throughout the inter-metal dielectric layers, which may lead to undesired characteristic change of the low-k dielectric materials. Due to the large exposed surface area of the TSV recesses, this detrimental effect can be significant and cause serious device performance degradation and yield loss.